IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION ( VLSI ) SYSTEMS 1 Synthesis of Pipelined DSP

نویسندگان

  • P. Schaumont
  • B. Vanthournout
  • I. Bolsens
  • H. De Man
چکیده

1 Synthesis of Pipelined DSP Accelerators with Dynamic Scheduling P. Schaumont, B. Vanthournout, I. Bolsens, H. De Man, Fellow, IEEE Abstract|To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology is presented to synthesize high throughput DSP functions into accelerator processors containing a datapath of highly pipelined, bit-parallel hardware units. Emphasis will be put on the de nition of a controller architecture that allows e cient run-time schedules of these DSP algorithms on such highly pipelined data paths. The methodology will be illustrated by means of an image encoding lter bank.

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Synthesis of Pipelined DSP Accelerators with Dynamic Scheduling - Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

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تاریخ انتشار 1997